/*	Title	Device Definitions and Equates*/
#define FMY_PAL_TYPE			0x0001			/* pal device type				*/
#define FMY_PROM_TYPE			0x0002			/* prom device type				*/
#define FMY_VERIFY_PHANTOMS		0x0080			/* verify phantom fuses 			*/
#define FMY_DEFAULT_BIT_STATE		0x0100			/* state of non programmed bits in proms/eproms */
#define FMY_CMOS_DEVICE 		0x2000			/* device is CMOS technology			*/
#define FMY_WARN_SECURE 		0x4000			/* manufacture warns of secured devices 	*/
#define FMY_GEN_PURPOSE_FLAG		0x8000			/* general purpose flag 			*/

#define DEV_ADDRESS_LATCH_ENABLE	0x0001			/* PROM requires ce/ale toggle on address change*/
#define DEV_PAGE_ADDRESSED		0x0002			/* page addressed PROMS 			*/
#define DEV_OUTPUT_POLARITY		0x0008			/* PAL contains fused output polarity		*/
#define DEV_REGISTERED_OUTPUTS		0x0010			/* PAL contains registered outputs		*/
#define DEV_JEDEC_ADDR_TRANSLATE	0x0020			/* JEDEC addr needs to be translated		*/
#define DEV_GEN_PURPOSE_FLAG		0x8000			/* general purpose flag 			*/

#define ARY_PHANTOM_ILNS		0x0001			/* PAL contains phantom ilns			*/
#define ARY_PHANTOM_PLNS		0x0002			/* PAL contains phantom plns			*/
#define ARY_PHANTOM_OUTPUTS		0x0004			/* PAL contains phantom outputs 		*/
#define ARY_DISPLAY_PHANTOMS		0x0008			/* display phantom product terms		*/
#define ARY_ILN_ADDR_TRANSLATE		0x0010			/* translate iln address			*/
#define ARY_PLN_ADDR_TRANSLATE		0x0020			/* translate pln address			*/
#define ARY_MULTIPLE_ADDR_SETS		0x0100			/* array addressing varies with geometry	*/
#define ARY_DEFAULT_PINS		0x0200			/* default pin values valid			*/
#define ARY_ACCUMULATE_PLN		0x0400			/* display accumulated pln number		*/
#define ARY_NON_JEDEC_ARRAY		0x0800			/* array is excluded in jedec file transfers	*/
#define ARY_SPECIAL_VOLTAGE		0x1000			/* array needs special voltage for read or write*/
#define ARY_GEN_PURPOSE_FLAG		0x8000			/* general purpose flag 			*/

#define MAX_INPUT_LINES 		72			/* maximum number of input lines		*/
#define MAX_PRODUCT_LINES		168			/* maximum number of product lines		*/
#define MAX_OUTPUT_LINES		14			/* maximum number of output lines		*/
#define MAX_PHANTOM_MAP 		MAX_PRODUCT_LINES / 8	/* maximum number of bytes for phantom map	*/
#define MAX_ARRAYS			16			/* maximum number of fuse arrays		*/
#define MAX_JEDEC_XLATE_ENTRIES 	50			/* maximum number of jedec pln xlation entries	*/

#define MAX_DEVICE_PINS 		48			/* maximum number of device pins		*/
#define MAX_USABLE_PINS 		40			/* maximum number of usable pins		*/
#define MAX_HALFS			2			/* maximum number of halfs			*/
#define MAX_PROGRAMMER_PINS		88			/* maximum number of programmer pins		*/
/**/
#define FUS_FUSE_STATE			0x01			/* map bit for the fuse 			*/
#define FUS_FUSE_TYPE_MASK		0x0E			/* mask for fuse type (if 0 => valid fuse)	*/
#define FUS_PHANTOM_OUTPUT		0x02			/* phantom output fuse				*/
#define FUS_PHANTOM_PLN 		0x04			/* phantom product line fuse			*/
#define FUS_PHANTOM_ILN 		0x06			/* phantom input line fuse			*/
#define FUS_PROG_PHANTOM_MASK		0x08			/* program phantom fuse mask			*/
#define FUS_PROG_PHANTOM_OUTPUT 	0x0A			/* program phantom output fuse			*/
#define FUS_PROG_PHANTOM_PLN		0x0C			/* program phantom product line fuse		*/
#define FUS_PROG_PHANTOM_ILN		0x0E			/* program phantom input line fuse		*/
#define FUS_INVERTED_OUTPUT		0x10			/* Inverted output fuse 			*/

#define DISCONNECT			0x00			/* disconnect pin from drivers			*/
#define DISCON_VAL			-2			/* table value */
#define HI_Z				0x50			/* high impedance				*/
#define HI_Z_VAL			-1			/* table value */

#define Z				0x50			/* high impedance				*/
#define Z_VAL				-1			/* table value */
#define N				0x80			/* no action					*/
#define T				0x00			/* disconnect					*/
#define T_VAL				-2			/* table value */
#define L				0x08			/* low level input voltage			*/
#define H				0x10			/* high level input voltage			*/
#define HH				0x06			/* high level program voltage vihh		*/
#define P				0x46			/* high level program voltage vpp		*/
#define V				0x01			/* high level voltage vcc			*/

#define LOOKUP_TABLE			0			/* lookup pin table designator			*/
#define BIN_ADDR			1			/* binary address designator			*/
#define UNARY_ADDR			2			/* unary adrress designator			*/
#define OUTPUT_ADDR			3			/* output address designator			*/
#define MMI_ILN_ADDR			100			/* MMI address iln designator			*/

/*	Subttl	Pin Number Equates*/
#define PIN01				1   /* pin # 1 */
#define PIN02				2   /* pin # 2 */
#define PIN03				3   /* pin # 3 */
#define PIN04				4   /* pin # 4 */
#define PIN05				5   /* pin # 5 */
#define PIN06				6   /* pin # 6 */
#define PIN07				7   /* pin # 7 */
#define PIN08				8   /* pin # 8 */
#define PIN09				9   /* pin # 9 */
#define PIN10			       10   /* pin #10 */
#define PIN11			       11   /* pin #11 */
#define PIN12			       12   /* pin #12 */
#define PIN13			       13   /* pin #13 */
#define PIN14			       14   /* pin #14 */
#define PIN15			       15   /* pin #15 */
#define PIN16			       16   /* pin #16 */
#define PIN17			       17   /* pin #17 */
#define PIN18			       18   /* pin #18 */
#define PIN19			       19   /* pin #19 */
#define PIN20			       20   /* pin #20 */
#define PIN21			       21   /* pin #21 */
#define PIN22			       22   /* pin #22 */
#define PIN23			       23   /* pin #23 */
#define PIN24			       24   /* pin #24 */
#define PIN25			       25   /* pin #25 */
#define PIN26			       26   /* pin #26 */
#define PIN27			       27   /* pin #27 */
#define PIN28			       28   /* pin #28 */
#define PIN29			       29   /* pin #29 */
#define PIN30			       30   /* pin #30 */
#define PIN31			       31   /* pin #31 */
#define PIN32			       32   /* pin #32 */
#define PIN33			       33   /* pin #33 */
#define PIN34			       34   /* pin #34 */
#define PIN35			       35   /* pin #35 */
#define PIN36			       36   /* pin #36 */
#define PIN37			       37   /* pin #37 */
#define PIN38			       38   /* pin #38 */
#define PIN39			       39   /* pin #39 */
#define PIN40			       40   /* pin #40 */

#define READ				0
#define BLANK				1
#define VERIFY				2
#define PROGRAM 			3
#define SECURE				4
#define PRELOAD 			5

/*	Subttl	User Function Return Equates*/
#define FAIL				-1			/* function failed				*/
#define DONE				0			/* exit function returned true			*/
#define PASS				1			/* function returned normally			*/
#define WAIT				2			/* function requests message window left alone	*/
#define NOHLP				3			/* no help for function 			*/

/*	Subttl	Data Structure*/
struct data_struc
{
    unsigned int data_segment;
    unsigned int data_width;
};

struct function_struc
{
    unsigned char function_name [9];
    int (*function_address) ();
};

struct index_struc
{
    int index_field;
    unsigned char *index_record_ptr;
};

/*	Subttl	Device Structure*/
struct device_struc
{
    unsigned char device_name [30];
    unsigned char device_description [80];
    unsigned char device_family_type [30];
    unsigned char device_id;
    unsigned int device_flags;
    unsigned int number_of_arrays;
    unsigned char device_array_name [30];
    int jedec_to_int_xlate_table [4] [MAX_JEDEC_XLATE_ENTRIES];
};

/*	Subttl	Family Structure*/
struct family_struc
{
    unsigned char manufacture_name [30];
    unsigned char function [9];
    unsigned char manufacture_id;
    unsigned int family_flags;
    int device_vil;
    int device_vih;
    int device_vihh;
    int device_vpp;
    int device_1st_verify_vcc;
    int device_2nd_verify_vcc;
    int slew_rate;
    int slew_delay;
    int program_pulse;
    unsigned int device_pins;
    int verify_passes;
    int retries;
    unsigned char vcc_pin_table [MAX_HALFS] [(MAX_USABLE_PINS / 4) + 1];
    unsigned char shut_down_pin_table [MAX_HALFS] [MAX_USABLE_PINS + 1];
    int device_vcc_secure;
    int device_vil_secure;
    int device_vihh_secure;
    int secure_retries;
    int secure_program_pulse;
    unsigned char sequence_secure_pin_table [MAX_HALFS] [MAX_USABLE_PINS + 1];
};

/*	Subttl	Array Structure*/
struct array_struc
{
    unsigned char array_description [80];
    unsigned int array_flags;
    unsigned int bits_per_address;
    unsigned int starting_fuse_number;
    unsigned int number_of_valid_fuses;
    int special_voltage_1;
    int special_voltage_2;
    int special_voltage_3;
    unsigned int outputs;
    unsigned int output_pins;
    unsigned int outputs_per_access;
    unsigned char output_pin_table [MAX_HALFS] [(MAX_USABLE_PINS / 2) + 1];
    unsigned int plns;
    unsigned int pln_pins;
    unsigned char pln_pin_table [MAX_HALFS] [(MAX_USABLE_PINS / 2) + 1];
    int pln_addr_xlat_table [MAX_PRODUCT_LINES];
    unsigned int ilns;
    unsigned int iln_pins;
    unsigned char iln_pin_table [MAX_HALFS] [(MAX_USABLE_PINS / 2) + 1];
    int iln_addr_xlat_table [MAX_INPUT_LINES];
    unsigned char default_pin_states [MAX_HALFS] [MAX_USABLE_PINS + 1];
    unsigned char int_down_pin_table [MAX_HALFS] [MAX_USABLE_PINS + 1];
    unsigned char sequence1_pin_table [MAX_HALFS] [(MAX_USABLE_PINS / 2) + 1];
    unsigned char sequence2_pin_table [MAX_HALFS] [(MAX_USABLE_PINS / 2) + 1];
    unsigned char sequence3_pin_table [MAX_HALFS] [(MAX_USABLE_PINS / 2) + 1];
    unsigned char sequence4_pin_table [MAX_HALFS] [(MAX_USABLE_PINS / 2) + 1];
    unsigned char phantom_iln_map [MAX_PHANTOM_MAP];
    unsigned char phantom_program_iln_map [MAX_PHANTOM_MAP];
    unsigned char phantom_prog_data_iln_map [MAX_PHANTOM_MAP];
    unsigned char phantom_pln_map [MAX_PHANTOM_MAP];
    unsigned char phantom_program_pln_map [MAX_PHANTOM_MAP];
    unsigned char phantom_prog_data_pln_map [MAX_PHANTOM_MAP];
    unsigned char phantom_out_map [MAX_PHANTOM_MAP];
    unsigned char phantom_program_out_map [MAX_PHANTOM_MAP];
    unsigned char phantom_prog_data_out_map [MAX_PHANTOM_MAP];
    unsigned char out_invert_map [MAX_PHANTOM_MAP];
};

/*	Subttl	Standard Externals*/
extern struct device_struc device;
extern struct family_struc family;
extern struct array_struc array [];
